| 1 |
Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing |
| 2 |
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC |
| 3 |
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block |
| 4 |
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule |
| 5 |
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks |
| 6 |
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme |
| 7 |
Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM |
| 8 |
A 65 nm Cryptographic Processor for High Speed Pairing Computation |
| 9 |
VLSI Design for SVM-Based Speaker Verification System |
| 10 |
Low-Power Programmable PRPG With Test Compression Capabilities |
| 11 |
11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids |
| 12 |
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT |
| 13 |
A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors |
| 14 |
A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks |
| 15 |
A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification |
| 16 |
A Synergetic Use of Bloom Filters for Error Detection and Correction |
| 17 |
An 8-bit 100-GS/s Distributed DAC in 28-nm CMOS for Optical Communications |
| 18 |
An 8-bit 100-GS/s Distributed DAC in 28-nm CMOS for Optical Communications |
| 19 |
An Implantable Versatile Electrode-Driving ASIC for Chronic Epidural Stimulation in Rats |
| 20 |
Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover |
| 21 |
Economizing TSV Resources in 3-D Network-on-Chip Design |
| 22 |
Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs |
| 23 |
Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications |
| 24 |
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels |
| 25 |
Majority-Based Test Access Mechanism forParallel Testing of Multiple Identical Cores |
| 26 |
Novel VLSI Architecture for Real Time Medical Image Segmentation |
| 27 |
Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels |
| 28 |
Partially Parallel Encoder Architecture for Long Polar Codes |
| 29 |
Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs |
| 30 |
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures |
| 31 |
An 8T Low-Voltage and Low-Leakage
Half-Selection Disturb-Free SRAM Using
Bulk-CMOS and FinFETs |
| 32 |
Drowsy Driver Detection using Representation Learning |
| 33 |
Information Hiding as a Challenge for Malware Detection |
| 34 |
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit |
| 35 |
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology |
| 36 |
Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication |
| 37 |
VLSI Computational Architectures for the Arithmetic Cosine Transform |
| 38 |
A New Data Transfer Method via Signal-Rich-Art Code Images Captured by Mobile Devices |
